In current metal oxide semiconductor field effect transistors (MOSFETs), a polysilicon gate is typically employed. One disadvantage of utilizing polysilicon gates is that at inversion, the polysilicon gates generally experience depletion of carriers in the area of the polysilicon gate that is adjacent to the gate dielectric. This depletion of carriers is referred to in the art as the polysilicon depletion effect. The depletion effect reduces the effective gate capacitance of the MOSFET. Ideally, it is desirable that the gate capacitance of the MOSFET be high since high gate capacitance typically equates to more charge being accumulated. As more charge is accumulated in the channel, the source/drain current becomes higher when the transistor is biased.
MOSFETs including a gate stack comprising a bottom polysilicon portion and a top silicide portion are also known. The layer of silicide in such a gate stack contributes to a decrease in the resistance of the gate. The decrease in resistance causes a decrease in the time propagation delay RC of the gate. Although a silicide top gate region may help decrease the resistance of the transistor, charge is still depleted in the vicinity of the interface formed between the bottom polysilicon gate and gate dielectric, thereby causing a smaller effective gate capacitance.
Another type of MOSFET that is available is one where the gate electrode is made entirely of a metal. In such MOSFETs, the metal of the gate prevents depletion of charge through the gate. This prevents the increase in effective thickness of the gate capacitor and the capacitance increases as a result of the depletion effect.
Although metal gates can be used to eliminate the poly-depletion effect and to provide lower gate resistance, it is generally quite difficult to offer multiple-threshold voltages with metal gates. Multiple-threshold voltages are needed in the semiconductor industry in order to provide design flexibility for low-power, high-performance, and mixed-signal applications for overall system performance. That is, it is difficult to tailor metal gate stacks such that the workfunction thereof meets a desired value for application in a specific device area.
In addition to metal gates, fully silicided metal gates are also known. For example, U.S. Pat. No. 6,204,103 to Bai, et al. discloses a method for forming first and second transistor devices having fully silicided gates. This prior art method includes the steps of forming a first region of silicide over a portion of a gate dielectric that overlies a first well region in a semiconductor substrate; forming a second region of silicide over a second portion of the gate dielectric that overlies a second well region in the substrate; and forming first and second doped regions in the first and second well regions.
U.S. Pat. No. 6,846,734 to Amos et al. discloses another example of a process of forming fully silicided metal gates. In the process disclosed in Amos et al., total silicidation of the gate electrode is achieved utilizing a metal bilayer or a metal alloy layer that is formed upon a Si-containing gate material.
Although technologies exist for forming fully silicided gate electrodes, there exists a need for providing alternative approaches for forming such fully silicided gate electrodes. In particular, a method is needed that enables full silicidation (FUSI) of the gate electrode at the same time as silicidation of the source/drain regions. In addition, a method is also needed that creates different fully silicided gate electrodes of different heights and different phases in each of the device regions that are present within a semiconductor substrate such that the fully silicided gates are tailored to provide a desired workfunction within the specific device region.